1. Field of the Invention
The present invention relates to the components of an electrical package and a fabricating method thereof. More particularly, the present invention relates to an electrical package of high reliability, an interposer thereof, a contact structure on a substrate, and a fabricating method of the contact structure.
2. Description of Related Art
The operation speed of chips has been improved continuously along with the development in the fabrication technique of integrated circuits (IC), thus, the process and calculation of various digital data has become very efficient. However, along with the drastic increase in the integration of chip's internal circuit, the heat produced by an electrical package carrying the chip has increased accordingly, thus, the problem of improper operation of package device due to thermal stress is always incurred, and meanwhile, the reliability of the package device is affected.
A conventional electrical package includes a first level package of a bonded chip and chip carrier, and a second level package of the chip carrier carrying the chip and a circuit board. Due to the difference in coefficient of thermal expansion (CTE) between the chip, the chip carrier, and the circuit board, different thermal strains may be produced because of different operation temperatures between components of the package during the packaging process or the reliability testing and actual operation thereafter. In recent years, a packaging technique for directly bonding a chip and a circuit board is developed to meet the requirement in the design of light, thin, short, and small electrical packages. The bonding between the chip and the circuit board is damaged even more easily by stress because the difference in CTEs of the chip and the circuit board is even larger, accordingly the reliability of the product is affected.
Presently, there are two means for improving the reliability of the contact between an electronic device and a circuit board. Firstly, improvement is done to the electronic device, for example, devices are packaged as a ball grid array (BGA) type and the difference of CTEs between the electronic device and the circuit board is minimized via an organic substrate, or a wafer level package with a compliant layer is proposed for the electronic device. On the other hand, a special structure can be designed on the circuit board for eliminating stress.
A contact structure for eliminating stress is disclosed in U.S. Pat. No. 4,893,172. FIG. 1A shows the contact structure. FIG. 1B is a cross-sectional view of the contact structure. FIG. 1C is a cross-sectional view of the contact structure which is deformed by stress. Referring to FIGS. 1A˜1C, the contact structure 100 includes a flat helical conductor 120 disposed on a dielectric layer substrate 110. One end of the helical conductor 120 is connected to the solder pad 140 on the electronic device 130, and the other end of the helical conductor 120 is connected to the solder pad 160 on the circuit board 150. The deformation of the helical conductor 120 can absorb the horizontal or vertical stress deformation caused by CTE difference between the electronic device 130 and the circuit board 150.
Another contact structure for eliminating stress is disclosed in U.S. Pat. No. 5,763,941. FIG. 2A is a cross-sectional view of the contact structure. FIG. 2B is a cross-sectional view of the contact structure which is deformed by stress. Referring to FIGS. 2A˜2B, the contact structure 200 includes a lead 220 disposed on a dielectric substrate 210, wherein the lead 220 can be separated into two parts, one end of the lead 220 is fixed on the dielectric substrate 210, and the other end of the lead 220 is connected to the electronic component 230. A compliant material can be further filled between the dielectric substrate 210 and the electronic component 230 for protecting the lead 220.